Cam reference for inspection of multi-color and contour images

ABSTRACT

This invention discloses an electrical circuit inspection system including an optical subsystem for optically inspecting an electrical circuit and providing an inspection output identifying more than two different types of regions and an analysis subsystem for analyzing the inspection output, the analyzing including comparing the inspection output with a computer file reference identifying more than two different types of regions. A method for inspecting an electrical circuit inspection is also disclosed.

FIELD OF THE INVENTION

[0001] The present invention relates to automated optical inspection(“AOI”) systems generally, and in particular to AOI systems whichcompare the image of a pattern under inspection, such as patterns foundon electrical circuits, to a reference.

BACKGROUND OF THE INVENTION

[0002] Apparatus and methods for automatically inspecting and analyzingimages of patterned articles by comparing the images to a computergenerated reference, are well known in the art.

[0003] By way of example, systems that are operative to automaticallyoptically inspect printed circuit boards by comparing images of aprinted circuit board under inspection to a computer generated referencethat is prepared from a computer aided manufacturing file, are generallycommercially available. One typical configuration of such a systemincludes an Xpert 1700™ computer aided manufacturing system, CDR 300™and Ref-Manager 300™ software appliances, and an Inspire 9000™ AOIsystem, all available from Orbotech Ltd. of Yavne, Israel.

[0004] Patterns inspected by conventional AOI systems typically areformed from copper conductors deposited on a non-conductive substrate.The patterns inspected are binary in nature inasmuch as only twooptically identifiable populations, copper conductor and substrate, areconsidered.

[0005] The following co-pending patent applications, which are assignedto the same assignee as the present application and which describeapparatus and methods suitable for automatically optically inspectingpatterned articles, such as electrical circuits, are hereby incorporatedherein by reference:

[0006] Israel Patent Application 131092, filed Jul. 25, 1999; and

[0007] Israel Patent Application 131282, filed Aug. 5, 1999.

[0008] In co-pending Israel patent applications 131092 and 131282,hardware and software parts of an automated optical inspection systemoperative to inspect non-binary patterns are described. Such non-binarypatterns may be found, for example, on the outer layer of a finishedprinted circuit board, ball grid array substrate, tape automated bondingsubstrate, or other similar carriers and chip packaging. Thesenon-binary patterns, in addition to an electrical circuit, includevarious exotic metal coatings on selected portions of the conductors andtranslucent solder masks that cover selected parts of the circuit.

[0009] Conventional computer generated references of binary images, suchas references typically used in the inspection of electrical circuits onprinted circuit boards, do not provide complete information about thelocation of multiple optically identifiable populations or combinationsof populations. Thus, for example, in the context of automated opticalinspection of the surface of a finished ball grid array substrate, whichtypically includes at least copper conductors deposited on a substrate,a translucent solder mask that partly covers the conductors and goldcoatings on some exposed portions of the conductors, conventional binaryreferences used in the automated optical inspection of electricalcircuits do not contain information about the existence, location andintegrity of gold coatings on conductors, or about the existence,location and integrity of solder mask relative to the conductors or thesubstrate.

[0010] Additionally, conventional computer generated references, such asreferences typically used in the inspection of electrical circuits onprinted circuit boards, typically provide information about pixel valuesfor individual pixels in an image and an electrical circuit to beinspected, or about the existence and location of features in theelectrical circuit. Information about the existence or location ofcontours and edges is not provided.

[0011] Although a reference useful for inspecting a pattern comprisingmultiple optically identifiable populations and/or contours and edgesmay be prepared from the actual inspection of a perfect or “golden”pattern, the use of a reference derived from actual inspection isproblematic. As readily is appreciated, the process of preparing areference from inspection of an article believed to have a perfectpattern is time consuming and necessitates large resources such ascomputer memory. Moreover, a reference prepared, for example, from acomputerized design file (a “CAD file”) or from a computerizedmanufacture file (a “CAM”) file can provide information not directlyavailable in a reference derived from actual inspection. For example,regions external to the electric circuit that do not require inspection,vias and step and repeat data may be available in a CAD file or CAMfile. Additionally, there is always uncertainty as to whether thepattern used to derive a golden reference from inspection of any articlewas indeed perfect.

[0012] The disclosures of all references mentioned above and throughoutthe present specification are hereby incorporated herein by reference.

SUMMARY OF THE INVENTION

[0013] The present invention seeks to provide an improved apparatus andmethod for optically inspecting articles and analyzing their images,especially but not exclusively color images. The apparatus and methodsof the present invention are believed to be particularly applicable toinspecting and analyzing images of a patterned article, and moreparticularly, applicable to analyzing images of a patterned articlewhich includes a plurality of elements that have characteristic opticalattributes.

[0014] Articles for which the apparatus and method of the presentinvention are particularly suited to inspect include the surfaces ofball grid array substrates (“BGA”), printed circuit board substrates,particularly printed circuit board substrates including multipleconductor materials, laminated printed circuit boards, lead frames, flatpanel displays, hybrid chip packaging substrates, tape automated bondingsubstrates, and other similar multi-material patterned articles; forsimplicity of description and without limiting the generality of theforegoing, such articles are also termed throughout the presentspecification and claims as “electrical circuits” and other grammaticalforms thereof.

[0015] A general aspect of the present invention relates to apparatusand methods for the optical inspection of the surfaces of articles, suchas electrical circuits, wherein a surface being inspected includes anon-binary pattern and is analyzed with reference to a computer filereference. The computer file reference may, for example, be constructedfrom a plurality of different computer files by producing a composite orsuperimposition of various computer files, each representing a differentpart of the electric circuit being inspected. The computer files mayrepresent, for ex-ample, various deposits or overlays of materials whichtogether comprise an electrical circuit or a single layer thereof. Inthe case of a single layer of an electrical circuit, the single layertypically comprises a top layer or inspectable surface suitable forbeing automatically optically inspected. For the sake of simplicity ofdescription, the term “layer” is also used in the present specificationand claims to include a deposit or overlay that together with additionaldeposits or overlays forms an inspectable surface.

[0016] Another general aspect of the present invention relates to anapparatus and method for automatically optically inspecting the surfacesof articles, such as electrical surfaces, wherein a surface of thearticle being inspected includes a pattern and is analyzed withreference to a computer file reference having a representation of edgecontours formed by the pattern.

[0017] Still another general aspect of the present invention relates toa computer file reference which includes information relating tomultiple populations, each having a different generally homogeneousoptical characteristic, in a pattern on the surface of an article beinginspected. The computer file reference preferably is constructed bysuperimposing various overlays, wherein each overlay is preferablybinary in that it represents the locations at which the material ispresent. The optical characteristic of a pixel is determined as afunction of which materials represented in the various superimposedoverlays are present at a pixel.

[0018] Another general aspect of the present invention relates to acomputer file reference which includes information relating to edgecontour elements present in a pattern, such as a pattern on the surfaceof an article being inspected. Contours elements, referred to herein asCELs, may be binary or color. A binary CEL is a CEL that represents anedge between any two different populations of generally homogeneousoptical characteristics. A color CEL is a CEL that represents an edgebetween any two different populations of generally homogeneous opticalcharacteristics, and in addition identifies the population on eitherside of the edge. CELs preferably are defined to within a sub-pixelaccuracy.

[0019] There is thus provided in accordance with a preferred embodimentof the present invention an electrical circuit inspection systemcomprising an optical subsystem for optically inspecting an electricalcircuit and providing an inspection output identifying more than twodifferent types of regions; and an analysis subsystem for analyzing saidinspection output, said analyzing including comparing said inspectionoutput with a computer file reference identifying more than twodifferent types of regions.

[0020] Further in accordance with a preferred embodiment of the presentinvention the optical subsystem is capable of optically inspecting morethan one layer of an electrical circuit and the two different types ofregions include regions located in more than one layer of the electricalcircuit.

[0021] Still further in accordance with a preferred embodiment of thepresent invention the two different types of regions include one or moreof an exposed metal region, a metal region covered by a translucentmaterial, an exposed substrate and a substrate covered by saidtranslucent material.

[0022] Moreover in accordance with a preferred embodiment of the presentinvention the translucent material is a solder mask. Additionally andalternatively, the translucent material is a polyamide layer.

[0023] Further in accordance with a preferred embodiment of the presentinvention the more than two different types of regions include anexposed first metal region, a first metal region covered by atranslucent material, an exposed second metal region, a second metalregion covered by a translucent material, an exposed substrate and asubstrate covered by said translucent material.

[0024] Still further in accordance with a preferred embodiment of thepresent invention the translucent material is a solder mask.Alternatively and additionally, the translucent material is a polyamidelayer.

[0025] Further in accordance with a preferred embodiment of the presentinvention the computer file reference identifying more than twodifferent types of regions comprises a composite of multiple computerfiles, each representing a different layer of said electrical circuit.

[0026] Alternatively in accordance with a preferred embodiment of thepresent invention the computer file reference identifying more than twodifferent types of regions comprises an overlay of multiple computerfiles, each representing a different layer of said electrical circuit.

[0027] Alternatively, in accordance with a preferred embodiment of thepresent invention the computer file reference identifying more than twodifferent types of regions comprises multiple computer files, eachrepresenting a different layer of said electrical circuit, superimposedin mutual registration.

[0028] Further in accordance with a preferred embodiment of the presentinvention the said computer file reference comprises a computer file ofat least one metal layer and at least one layer of a translucentmaterial overlying said at least one metal layer, superimposed in mutualregistration.

[0029] Still further in accordance with a preferred embodiment of thepresent invention the computer file reference is a polychromaticreference.

[0030] Moreover in accordance with a preferred embodiment of the presentinvention the inspection output is a polychromatic output.

[0031] Additionally in accordance with a preferred embodiment of thepresent invention the computer file reference comprises at least one CAMfile.

[0032] There is thus provided in accordance with a preferred embodimentof the present invention apparatus for constructing a computer filereference identifying more than two different types of regions on anelectrical circuit, the apparatus comprising a superimposer forsuperimposing in mutual registration at least two computer files, eachrepresenting a different portion of said electrical circuit.

[0033] Further in accordance with a preferred embodiment of the presentinvention the different types of regions are optically distinguishable.

[0034] Still further in accordance with a preferred embodiment of thepresent invention the portion is a layer of the electrical circuit, anda plurality of layers form an inspectable surface of the electricalcircuit.

[0035] Moreover, in accordance with a preferred embodiment of thepresent invention the more than two different types of regions includean exposed metal region, a metal region covered by a translucentmaterial, an exposed substrate and a substrate covered by saidtranslucent material.

[0036] Additionally, in accordance with a preferred embodiment of thepresent invention the translucent material is a solder mask.Alternatively, the translucent material is a polyamide layer.

[0037] Further in accordance with a preferred embodiment of the presentinvention the more than two different types of regions include anexposed first metal region, a first metal region covered by atranslucent material, an exposed second metal region, a second metalregion covered by a translucent material, an exposed substrate and asubstrate covered by said translucent material.

[0038] Additionally in accordance with a preferred embodiment of thepresent invention the translucent material is a solder mask.Alternatively the translucent material is a polyamide layer.

[0039] Still further in accordance with a preferred embodiment of thepresent invention the computer file reference identifying more than twodifferent types of regions comprises a composite of multiple computerfiles, each representing a different layer of said electrical circuit.

[0040] Moreover in accordance with a preferred embodiment of the presentinvention the said computer file reference identifying more than twodifferent types of regions comprises an overlay of multiple computerfiles, each representing a different layer of said electrical circuit.

[0041] Alternatively in accordance with a preferred embodiment of thepresent invention the said computer file reference identifying more thantwo different types of regions comprises multiple computer files, eachrepresenting a different layer of said electrical circuit, superimposedin mutual registration.

[0042] Further alternatively in accordance with a preferred embodimentof the present invention the said computer file reference comprises acomputer file of at least one metal layer and at least one layer of atranslucent material overlying said at least one metal layer,superimposed in mutual registration.

[0043] Still further in accordance with a preferred embodiment of thepresent invention the said computer file reference comprises at leastone CAM file.

[0044] There is thus provided in accordance with a another preferredembodiment of the present invention a computer file reference useful inan electrical circuit inspection system comprising at least one computeroriginated computer file representing more than two different types ofregions in said electrical circuit

[0045] Further in accordance with a preferred embodiment of the presentinvention regions are optically distinguishable.

[0046] Still further in accordance with a preferred embodiment of thepresent invention the at least one computer originated computer filerepresents more than two different types of regions in said electricalcircuit, wherein each region is one of: a material forming part of anelectrical circuit, a composite of at least two materials forming partof an electrical circuit.

[0047] Alternatively in accordance with a preferred embodiment of thepresent invention the at least one computer file comprises a combinationof multiple computer files, each file representing a different layer ofan electrical circuit, and wherein the reference identifies more thantwo different types of regions.

[0048] Further in accordance with a preferred embodiment of the presentinvention the at least one computer file is derived from multiplecomputer files, each computer file representing a different layer of anelectrical circuit, wherein the reference identifies more than twodifferent types of regions.

[0049] Still further in accordance with a preferred embodiment of thepresent invention the reference comprises an overlay of multiplecomputer files, each overlay representing a different layer of saidelectrical circuit.

[0050] Moreover in accordance with a preferred embodiment of the presentinvention the computer file reference which identifies more than twodifferent types of regions comprises multiple computer files, whereineach represents a different layer of said electrical circuit, and thecomputer files superimposed in mutual registration.

[0051] Additionally, in accordance with a preferred embodiment of thepresent invention the computer file reference includes a computer fileof at least one metal layer and at least one layer of a translucentmaterial overlying said at least one metal layer, superimposed in mutualregistration.

[0052] Further in accordance with a preferred embodiment of the presentinvention the computer file reference is a polychromatic reference.

[0053] Still further in accordance with a preferred embodiment of thepresent invention the inspection output is a polychromatic output.

[0054] There is thus provided in accordance with a preferred embodimentof the present invention a method for determining a contour element(CEL) in each of a plurality of big pixels forming an image, each bigpixel comprising an array of small pixels, the method comprising:

[0055] assigning an array of small pixels to each big pixel; performingthe following steps for each big pixel:

[0056] computing a difference of gradients sign (referred to as a DOGsign) at one vertex of the big pixel;

[0057] determining two cross points along two edges of the big pixel,each cross point representing a value crossover between pixels having afirst value and pixels having a second value;

[0058] determining DOG signs for remaining vertices of the big pixelbased on DOG values assigned to neighboring pixels of the big pixel; and

[0059] if at least one DOG sign at one vertex of the big pixel differsfrom at least one DOG sign at one other vertex of the big pixel:

[0060] determining remaining cross points along remaining edges of thebig pixel; and

[0061] assigning a CEL based on a result of the determining remainingcross points step.

[0062] There is thus provided in accordance with a preferred embodimentof the present invention a method for determining a color contourelement (CEL) in each of a plurality of big pixels forming an image,each big pixel comprising an array of small pixels, the methodcomprising:

[0063] assigning an array of small pixels to each big pixel;

[0064] performing the following steps for each big pixel:

[0065] determining a number of colors of small pixels comprised in thebig pixel;

[0066] if the number of colors is equal to one, concluding the method;

[0067] if the number of colors is greater than two, indicating that ajunction exists in the big pixel and terminating the method;

[0068] otherwise, the number of colors being two, performing thefollowing steps:

[0069] computing a difference of gradients sign (DOG sign) at one vertexof the big pixel;

[0070] determining two cross points along two edges of the big pixel,each cross point representing a value crossover between pixels having afirst value and pixels having a second value;

[0071] determining DOG signs for remaining vertices of the big pixelbased on DOG values assigned to neighboring pixels of the big pixel; and

[0072] if at least one DOG sign at one vertex of the big pixel differsfrom at least one DOG sign at one other vertex of the big pixel:

[0073] determining remaining cross points along remaining edges of thebig pixel; and

[0074] assigning a color CEL based on a result of the determiningremaining cross points step and on the colors of small pixels comprisedin the big pixel.

[0075] Further in accordance with a preferred embodiment of the presentinvention each color CEL defines an edge between two populations ofhomogeneous optical characteristics, and identifies the population oneither side of the color CEL.

[0076] There is thus provided in accordance with a preferred embodimentof the present invention an electrical circuit inspection methodcomprising optically inspecting an electrical circuit and providing aninspection output identifying more than two different types of regions;and analyzing said inspection output, said analyzing including comparingsaid inspection output with a computer file reference identifying morethan two different types of regions.

[0077] Further in accordance with a preferred embodiment of the presentinvention the method includes superimposing in mutual registration atleast two computer files, each representing a different layer of saidelectrical circuit.

[0078] There is thus provided in accordance with a preferred embodimentof the present invention apparatus for determining a contour element(CEL) in each of a plurality of big pixels in an image, each big pixelcomprising an array of small pixels, the apparatus comprising:

[0079] a pixel assigner operative to assign an array of small pixels toeach big pixel;

[0080] a CEL determiner operative, for each big pixel:

[0081] to compute a difference of gradients sign (DOG sign) at onevertex of the big pixel;

[0082] to determine two cross points along two edges of the big pixel,each cross point representing a value crossover between pixels having afirst value and pixels having a second value;

[0083] to determine DOG signs for remaining vertices of the big pixelbased on DOG values assigned to neighboring pixels of the big pixel; and

[0084] if at least one DOG sign at one vertex of the big pixel differsfrom at least one DOG sign at one other vertex of the big pixel:

[0085] to determine remaining cross points along remaining edges of thebig pixel; and

[0086] to assign a CEL based on a result of the determining remainingcross points step.

[0087] There is thus provided in accordance with a preferred embodimentof the present invention apparatus for determining a color contourelement (color CEL) in each of a plurality of big pixels in an image,each big pixel comprising an array of small pixels, the apparatuscomprising:

[0088] and assigner operative to assign an array of small pixels to eachbig pixel;

[0089] a color cel determiner operative, for each big pixel:

[0090] to determine a number of colors of small pixels comprised in thebig pixel;

[0091] if the number of colors is equal to one, to conclude the method;

[0092] if the number of colors is greater than two, to indicate that ajunction exists in the big pixel and terminating the method;

[0093] otherwise, the number of colors being two:

[0094] to compute a difference of gradients sign (DOG sign) at onevertex of the big pixel;

[0095] to determine two cross points along two edges of the big pixel,each cross point representing a value crossover between pixels having afirst value and pixels having a second value;

[0096] to determine DOG signs for remaining vertices of the big pixelbased on DOG values assigned to neighboring pixels of the big pixel; and

[0097] if at least one DOG sign at one vertex of the big pixel differsfrom at least one DOG sign at one other vertex of the big pixel:

[0098] to determine remaining cross points along remaining edges of thebig pixel; and

[0099] to assign a color cel based on a result of the determiningremaining cross points step and on the colors of small pixels comprisedin the big pixel.

[0100] There is thus provided in accordance with a preferred embodimentof the present invention an electrical circuit inspection systemincluding an optical subsystem for optically inspecting an electricalcircuit and providing an inspection output identifying edges between atleast two different regions in the electrical circuit; and an analysissubsystem for analyzing said inspection output, said analyzing includingcomparing said inspection output with a computer file referenceidentifying edges between at least two different regions.

[0101] Further in accordance with a preferred embodiment of the presentinvention the optical subsystem is capable of optically inspecting morethan one layer of an electrical circuit and said more than two differentregions include regions at more than one layer of said electricalcircuit.

[0102] Still further in accordance with a preferred embodiment of thepresent invention the more than two different regions include two ormore of an exposed metal region, a metal region covered by a translucentmaterial, an exposed substrate and a substrate covered by saidtranslucent material.

[0103] Still further in accordance with a preferred embodiment of thepresent invention the translucent material is a solder mask.Alternatively translucent material is a polyamide layer.

[0104] Moreover in accordance with a preferred embodiment of the presentinvention the more than two different regions include an exposed firstmetal region, a first metal region covered by a translucent material, anexposed second metal region, a second metal region covered by atranslucent material, an exposed substrate and a substrate covered bysaid translucent material.

[0105] Further in accordance with a preferred embodiment of the presentinvention the translucent material is a solder mask. Alternatively, thetranslucent material is a polyamide layer.

[0106] Still further in accordance with a preferred embodiment of thepresent invention the computer file reference identifying more than twodifferent regions, includes a composite of multiple computer files, eachrepresenting a different layer of the electrical circuit.

[0107] Additionally or alternatively the computer file referenceidentifying more than two different regions comprises an overlay ofmultiple computer files, each representing a different layer of saidelectrical circuit.

[0108] Preferably the computer file reference identifying more than twodifferent regions, includes multiple computer files, each representing adifferent layer of the electrical circuit, superimposed in mutualregistration.

[0109] Still further in accordance with a preferred embodiment of thepresent invention the computer file reference includes a computer fileof at least one metal layer and at least one layer of a translucentmaterial overlying the metal layer, superimposed in mutual registration.

[0110] Further in accordance with a preferred embodiment of the presentinvention the computer file reference is a polychromatic reference.

[0111] Additionally in accordance with a preferred embodiment of thepresent invention the inspection output is a polychromatic output.

[0112] Still further in accordance with a preferred embodiment of thepresent invention the computer file reference includes at least one CAMfile. Additionally or alternatively the computer file reference includesa plurality of CAM files.

[0113] There is also provided in accordance with yet another preferredembodiment of the present invention a method for electrical circuitinspection. The method includes optically inspecting an electricalcircuit and providing an inspection output identifying edges between atleast two different regions in the electrical circuit and analyzing theinspection output. The analysis includes comparing the inspection outputwith a computer file reference identifying edges between at least twodifferent regions.

[0114] Further in accordance with a preferred embodiment of the presentinvention the optical inspection includes optically inspecting more thanone layer of an electrical circuit and the more than two differentregions, including regions at more than one layer of the electricalcircuit.

[0115] Still further in accordance with a preferred embodiment of thepresent invention the more than two different regions include an exposedmetal region, a metal region covered by a translucent material, anexposed substrate and a substrate covered by the translucent material.

[0116] Additionally in accordance with a preferred embodiment of thepresent invention the translucent material is a solder mask.Alternatively the translucent material is a polyamide layer.

[0117] Further in accordance with a preferred embodiment of the presentinvention the more than two different regions include an exposed firstmetal region, a first metal region covered by a translucent material, anexposed second metal region, a second metal region covered by atranslucent material, an exposed substrate and a substrate covered bythe translucent material.

[0118] Still further in accordance with a preferred embodiment of thepresent invention the computer file reference identifying more than twodifferent regions includes a composite of multiple computer files, eachrepresenting a different layer of the electrical circuit.

[0119] Moreover in accordance with a preferred embodiment of the presentinvention the computer file reference identifying more than twodifferent regions includes an overlay of multiple computer files, eachrepresenting a different layer of the electrical circuit.

[0120] Further in accordance with a preferred embodiment of the presentinvention the computer file reference identifying more than twodifferent regions includes multiple computer files, each representing adifferent layer of said electrical circuit, superimposed in mutualregistration.

[0121] Still further in accordance with a preferred embodiment of thepresent invention the computer file reference includes a computer fileof at least one metal layer and at least one layer of a translucentmaterial overlying the at least one metal layer, superimposed in mutualregistration.

[0122] Additionally in accordance with a preferred embodiment of thepresent invention the computer file reference is a polychromaticreference. Alternatively, the inspection output is a polychromaticoutput.

[0123] Further in accordance with a preferred embodiment of the presentinvention the computer file reference includes at least one CAM file.Additionally or alternatively the computer file reference includes aplurality of CAM files.

BRIEF DESCRIPTION OF THE DRAWINGS

[0124] The present invention will be understood and appreciated morefully from the following detailed description, taken in conjunction withthe drawings in which:

[0125]FIG. 1A is a simplified block diagram illustration of anelectrical circuit inspection system constructed and operative inaccordance with a preferred embodiment of the present invention;

[0126]FIG. 1B is a simplified pictorial illustration of an electricalcircuit, useful in understanding the present invention;

[0127]FIG. 2 is a simplified block diagram of a preferred implementationof a portion of the system of FIG. 1 illustrating construction of acomputer file reference;

[0128]FIG. 3 is a simplified flow chart illustrating a preferred methodof operation of the system of FIG. 1;

[0129]FIG. 4 is a simplified flow chart illustrating operation of partof the system of FIG. 1, shown in FIG. 2, which relates to generation ofa computer file reference;

[0130] FIGS. 5A-5C are simplified pictorial illustrations of examples ofoverlays, which may be combined together to comprise an inspectablesurface of an electrical circuit;

[0131]FIG. 5D is a simplified pictorial illustration of an example of aninspectable surface of an electrical circuit, which may be comprised ofthe overlays of FIGS. 5A-5C; and

[0132]FIG. 6 is a simplified pictorial illustration of the combinationof the overlays of FIGS. 5A-5C to comprise the inspectable surface ofFIG. 5D;

[0133]FIG. 7 is a simplified flowchart illustration of a preferredmethod of operation of a portion of the apparatus of FIG. 2, whichrelates to binary CEL generation;

[0134]FIG. 8 is a simplified pictorial illustration of a big pixel,comprising a plurality of small pixels, useful in understanding themethod of FIG. 7;

[0135]FIG. 9 is a simplified pictorial illustration of a big pixel andits neighbors, useful in understanding the method of FIG. 7; and

[0136]FIG. 10 is a simplified flowchart illustration of a preferredmethod of operation of a portion of the apparatus of FIG. 2, whichrelates to color CEL generation.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0137] Reference is now made to FIG. 1A which is a simplified blockdiagram illustration of an electrical circuit inspection systemconstructed and operative in accordance with a preferred embodiment ofthe present invention. The system of FIG. 1A preferably includes anoptical inspection subsystem 100, suitable for the inspection ofarticles such as electrical circuits. The optical inspection subsystem100 preferably is operative to provide an inspection output identifyingmore than two different types of regions in an inspected electricalcircuit. Additionally, optical inspection subsystem 100 preferably isoperative to provide an inspection output identifying edges, orcontours, between at least two different types of regions in aninspected electrical circuit.

[0138] The term “types of regions”, as used throughout the presentspecification and claims, may refer, for example, to any of thefollowing or similar types of regions:

[0139] 1. A plurality of regions of different color characteristics.

[0140] 2. A plurality of regions of different material or of differentlayers of material generally.

[0141] 3. A plurality of regions including, for example, an exposedmetal region, an exposed metal region coated by an exotic metal, a metalregion covered by a translucent material, an exposed substrate regionand a substrate region covered by a translucent material; thetranslucent material may be, for example, a polyamide layer or soldermask.

[0142] Reference is now additionally made to FIG. 1B, which is asimplified pictorial illustration of an electrical circuit, useful inunderstanding the present invention. The following description of FIG.1B will assist in understanding the term “types of regions” as describedabove.

[0143] The apparatus of FIG. 1B is intended to provide a particularexample of an article which may be optically inspected and analyzedusing the present invention. The example of FIG. 1B is not meant to belimiting.

[0144] The apparatus of FIG. 1B comprises an electrical circuit 101,comprising in the example of FIG. 1B a ball grid array (BGA) substrate.The BGA 101, as is well known in the art, typically comprises: regionsof copper conductor which are covered by a partially transparent ortranslucent coating such as a solder mask 102, regions of bare substrate103, regions of substrate covered by partially transparent ortranslucent solder mask 104, regions of copper conductor coated with ametal plating such as gold, for example balls 105 and power lines 106.Additionally, some of the regions plated with gold may also be coveredby partially transparent or translucent solder mask, such as coveredballs 107.

[0145] It is appreciated that each of the regions of different materialsand combinations of materials described hereinabove are characterized bya distinguishable color population. For example, regions of bare copperand gold plated copper are distinguishable by color. Solder-masktypically is green, and copper covered by solder mask typically is ashade of light green, gold plated copper covered by solder masktypically is a shade of very light green, and substrate covered bysolder mask typically is a shade of dark green. It is appreciated thatsolder mask and other materials and combinations of materials present onan electrical circuit may be other colors.

[0146] As described in co-pending Israel Patent Application 131092,filed Jul. 25, 1999, which has been incorporated herein by reference,each of the different color populations associated with a material orcombination of materials can be identified, and one or more of thefollowing representations may be produced to represent a region ofuniform color population: binary contour elements (contour elements arereferred to herein as “CELs”), representing a boundary or edge betweenany two color populations; color CELs, representing a boundary or edgebetween any two color populations and identifying the respective colorpopulations therealong; morphology features, representing the skeletonshape of a color population; and color morphology features representingthe skeleton shape of a color population and identifying the respectivecolor population.

[0147] It is appreciated that a wide variety of suitable imageprocessing and analysis systems may be used as the optical inspectionsubsystem 100. The software and hardware parts of one particular exampleof a suitable image processing and analysis system is described in thefollowing co-pending applications which are assigned to the assignee ofthe present application, the disclosures of which have been incorporatedherein by reference:

[0148] Israel Patent Application 131092, filed Jul. 25, 1999; and

[0149] Israel Patent Application 131282, filed Aug. 5, 1999.

[0150] Referring back to FIG. 1A, the optical inspection subsystem 100receives for inspection an electrical circuit 110, such as the BGA 101shown in FIG. 1B. Although, electrical circuit 110 is depicted in FIG.1A, by way of example only, as a BGA, it is appreciated that anysuitable electrical circuit, or other suitable patterned article, may beinspected.

[0151] The system of FIG. 1A also preferably includes an analysissubsystem 120, typically implemented in a suitable combination ofsoftware and general-purpose hardware. The analysis subsystem 120 mayalso include, at least in part, special purpose hardware for optimumperformance.

[0152] The analysis subsystem 120 preferably receives the inspectionoutput for the electrical circuit 110 being inspected from the opticalinspection subsystem 100, designated an “online” inspection output, andpreferably is operative to analyze the online inspection output withreference to a computer file reference 130. The computer file reference130 preferably identifies more than two different types of regions, suchas more than two regions of uniform color population, and edge contoursbetween the various regions, as described above. Thus, the analysissubsystem 120 preferably is operative to analyze the online inspectionoutput, at least in part by comparing and analyzing the inspectionoutput, which preferably identifies CELs, features and more than twodifferent types of regions, with the computer file reference 130, whichalso preferably identifies CELs, features and more than two differenttypes of regions, and to produce a result of the analysis.

[0153] Preferably, the result produced by the analysis subsystem 120includes an indication of differences between the inputs to the analysissubsystem 120. In a preferred implementation of the present invention,the computer file reference 130 is representative of an ideal form ofthe electrical circuit 110, and the result produced by the analysissubsystem 120 represents deviations or errors in the online inspectionoutput for electrical circuit 110 as compared to the idealrepresentation.

[0154] The computer file reference 130 preferably comprises a computeroriginated computer file. The term “computer originated computer file”is used herein to refer to a computer file such as a computer-aidedmanufacturing (CAM) file, a computer-aided design (CAD) file, and anyother appropriate type of computer file which may originate in acomputer and in interaction between a computer and a user thereof. Theterm “computer originated computer file” is intended to exclude areference file derived from inspection of an article believed to be anot defective or a “golden” article, such as a computer file derivedfrom an optical inspection system of the type described above withreference to the optical inspection subsystem 100.

[0155] Preferably, at least a portion of the computer file reference 130has a format similar to that of at least a portion of the inspectionoutput of the optical inspection subsystem 100, thus allowing theanalysis subsystem 120 to operate more efficiently, in performing ananalysis as described above, for example by comparing similar data.Alternatively, it is appreciated that the analysis subsystem 120 may beoperative to convert one or both of the computer file reference 130 andthe inspection output of the optical inspection subsystem 100 into asimilar or common format. Further alternatively, a compatible conversionunit (not shown) may be provided separately to perform the conversion.

[0156] It is appreciated that the analysis subsystem 120 preferably isoperative to register the computer file reference and the onlineinspection outputs. Methods for dynamically registering onlineinspection outputs to a reference are well known in the art. A preferredmethod for dynamically registering online inspection outputs and acomputer file reference is described in U.S. Pat. No. 5,495,535 to Harelet al., the disclosure of which is incorporated here by reference.

[0157] The computer file reference 130 preferably is produced by acomputer file reference constructor 140. The computer file referenceconstructor 140 preferably is operative to produce the computer filereference 130 from a plurality of inputs. The plurality of inputs to thecomputer file reference constructor 140 preferably comprises a pluralityof files, such as CAM files, each describing one overlay correspondingto part of a design of a layer of the electrical circuit 110. The layermay be, for example, a single layer, such as the outer layer of amulti-layered circuit. First, second and third computer files 144, 146,and 148, representing respectively first, second, and third overlays,are shown by way of example only. The computer file referenceconstructor 140 may produce the computer file reference 130 using anyappropriate method, such as by producing a composite or superimposition,particularly a superimposition in mutual registration, of the computerfiles 144, 146, and 148.

[0158] Reference is now made to FIG. 2, which is a simplified blockdiagram of a preferred implementation of a portion of the system of FIG.1A illustrating the preparation of a computer file reference. Theapparatus of FIG. 2 comprises a preferred implementation of the computerfile reference constructor 140 of FIG. 1A. It is appreciated that otherpreferred implementations are possible, and that the implementation ofFIG. 2 is by way of example only, and is not meant to be limiting.

[0159] The components of the computer file reference constructor 140 aretypically implemented in a combination of hardware and software, as iswell known in the art.

[0160] The apparatus of FIG. 2 preferably comprises a CAM workstation150. CAM workstation 150 may comprise any suitable computer workstation,preferably running a commercially available CAM software package forelectrical circuit manufacture, such as Xpert™ 1700 CAM softwarecommercially available from Orbotech Ltd. The CAM workstation 150typically is operative, as is well known in the art, to receive as inputCAD data and to produce therefrom CAM data, typically in a vector formatused in the operation of electrical circuit manufacturing equipment.

[0161] The input CAD data may be in any appropriate format such as, forexample, in Gerber format, which is well known in the art of PCBmanufacturing for use with computer aided manufacturing files used inimaging systems. The vector format CAM data may be in any appropriateformat, such as aoiimg or opf format, which formats are CAM formatswidely used in PCB manufacturing. In the present invention, the CAM data(or the CAD data, whichever is used) preferably comprises data defininga plurality of overlays which together form a layer of an electricalcircuit, such as the top or outer layer of a BGA. For example, andwithout limiting the generality of the foregoing, the CAM data maycomprise computer files 144, 146, and 148 of FIG. 1A.

[0162] The apparatus of FIG. 2 also preferably comprises a vector/rasterconversion unit 160. The vector/raster conversion unit 160 may compriseany appropriate unit operative to receive a vector format input andproduce a raster format output which forms an image having a pluralityof pixel locations and preferably specifies a state for each pixel, suchas a binary state designating that each pixel is black or white.Alternatively, a non binary state may be specified. Vector to rasterconversion is well known in the art.

[0163] It is appreciated that the actual resolution at which imageanalysis is performed by the inspection subsystem 100 (FIG. 1A)preferably is finer than the optical resolution at which it acquiresimages of an article being inspected. Accordingly, it is necessary toconstruct the computer file reference 130 to the level of higherresolution at which image analysis is to be performed by imageinspection subsystem 100.

[0164] It is appreciated that, alternatively to the CAM station 150, thevector/raster conversion unit 160, and the superimposer 170 describedbelow, other apparatus and/or other means may be used to directlygenerate raster format data for each of the layers or overlays. Forexample, the raster format data may be produced directly such as, forexample, in a CAM process (not shown), and then supplied to the othercomponents of FIG. 2.

[0165] Preferably, the output of the vector/raster conversion unit 160is received by a binary CEL producer and skeleton producer 174, as wellas by the superimposer 170 as described below. The binary CEL producerand skeleton producer 174 preferably is operative to produce binary CELsand skeleton information from the received input. A binary CELpreferably is a CEL defining an edge between any two differenthomogeneous color populations in an image. A homogeneous colorpopulation is a region having a distinctly identifiable opticalattribute such as a reflectivity or a color and generally may becorrelated to a material or combination of materials. A skeleton is amorphological skeleton of region, produced for example by erosiondilation techniques.

[0166] Methods for producing binary CELs and skeleton information frompixels in images are described in co-pending Israel Patent Application131092, filed Jul. 25, 1999, which has been incorporated herein byreference. Another preferred method for producing binary CELs fromraster format information is described in more detail below withreference to FIG. 7.

[0167] The apparatus of FIG. 2 also comprises a superimposer 170. Thesuperimposer 170 preferably is operative to superimpose raster formatdata received from several sources. The data is received from thevector/raster conversion unit 160 . Preferably each source, such as acomputer file overlay 144, 146 and 148 (FIG. 1A) represents one ofvarious separate deposits or overlays of materials that together withadditional information, such as ASCII information describing thelocation of drilled holes, masked areas not to be inspected and the like(not shown), describe a single layer or inspectable surface of anarticle to be inspected, such as the top or outer layer of a finishedBGA. Thus, for example, as described in greater detail hereinbelow withreference to FIGS. 5A-5D, one source describes regions of copperconductors, one source describes regions of gold plating on copperconductors, and one source describes regions of a solder mask overlay.Preferably, the deposits or overlays are superimposed in mutualregistration.

[0168] Further preferably, the superimposer 170 is operative to producean output comprising at least a polychromatic image, also termed hereina color image or a full color raster image, of the electrical circuit.In the polychromatic image, each pixel in the raster is assigned one ofa preselected number of colors as a function of which layer, orcombination of layers, provides data at the given pixel. Thepolychromatic image preferably is received by a masks producer 182,which also preferably receives ASCII format data output by the CAMstation 150 and CEL format information of one or more layers oroverlays, and preferably is operative to produce a mask therefromdefining regions not be inspected.

[0169] The superimposer 170, in producing the output thereof, such as acolor raster image, preferably takes into account predefined rulesgoverning the result of superimposing various overlays in differentways, and assigns a uniquely identifiable color population to eachcombination of materials represented by the overlays. The rulespreferably incorporate information about the relationship betweenoverlays. For example, if overlays are inputs defining regions of copperconductor, solder mask and gold coatings on conductors respectively, thefollowing rules might be comprised in the predefined rules fordetermining a color population to be assigned to a pixel:

[0170] Conductor+no solder mask+no gold coating=copper

[0171] No conductor+no solder mask+no gold coating=bare substrate

[0172] Conductor+solder mask+no gold coating=solder mask over copper

[0173] Conductor+solder mask+gold coating=solder mask over gold

[0174] No Conductor+solder mask+no gold coating=solder mask oversubstrate

[0175] The polychromatic image is also preferably received by a colorCEL/color skeleton producer 178, whose operation preferably is similarto that of the binary CEL producer and skeleton producer 174 and isdescribed in more detail below with reference to FIG. 10.

[0176] The superimposer 170 is also operative to produce binary datasuch as binary CEL data, that is, two-value data defining a contour oran edge between any two different homogeneous color populations,representing a “golden” or perfect example, of an image to be inspected.The binary golden data preferably is received by a binary CEL producerand skeleton producer 174, whose operation preferably is as describedabove.

[0177] Preferably, the outputs of binary CEL producer and skeletonproducers 174, the color CEL/color skeleton producer 178, and the masksproducer 182 emulate a representation of an article being inspected asgenerated by optical inspection subsystem 100. These outputs are inputinto a learn process 186 which preferably is operative to producetherefrom the computer file reference 130 which includes, for example, asuitable vectorized representation of collections of CELs or othersuitable representation of features in the electrical circuit that areusable as a reference in an inspection system. A preferredimplementation of the learn process 186 is described in detail inco-pending Israel Patent Application 131282, filed Aug. 5, 1999, whichhas been incorporated herein by reference.

[0178] Reference is now made to FIG. 3, which is a simplified flow chartillustrating a preferred method of operation of the system of FIG. 1A.The method of FIG. 3 preferably comprises the following steps:

[0179] A computer file reference is constructed from computer filesrepresenting layers of electrical circuit design (step 190) andpreferably is stored offline in a memory. An electric circuit isanalyzed using optical inspection (step 200) and an online inspectionoutput is generated. As described above with reference to FIG. 1A,preferably an output of step 200 and the computer file referenceproduced by step 190 preferably have compatible formats.

[0180] The results of the optical inspection are analyzed, typicallyincluding comparison with the computer file reference such as bymatching corresponding binary CELs and color CELs in electrical circuitsbeing inspected to binary CELs and color CELs in computer file reference(step 210). Analysis and comparison typically takes place onlineconcurrent to optical inspection. An inspection result 215 preferably isproduced, typically indicating one or more flaws, if present, in theoutput of step 190 as compared to the output of step 200.

[0181] Reference is now made to FIG. 4, which is a simplified flow chartillustrating operation of part of the system of FIG. 1A, shown in FIG.2, which relates to generation of a computer file reference. The methodof FIG. 4 preferably includes the following steps:

[0182] CAD data representing overlays that together form a layer of anelectrical circuit is received (step 220) and converted to CAM data,typically to CAM data in a vector format (step 230). The vector formatCAM data for each overlay is converted to raster format (step 240).Steps 220, 230, and 240 may be omitted if raster format data for eachoverlay is supplied initially.

[0183] Data representing each of the overlays in the raster format datais mutually superimposed, to produce a representation of a layer of anelectrical circuit to be inspected (step 250), preferably comprising acolor raster image in which the various homogeneous color populationsresulting from combination of overlays are represented. The homogeneouscolor populations preferably are assigned according to predeterminedrules as described hereinabove with reference to superimposer 170 inFIG. 2. Data, including the output of step 250 as well as the output ofstep 230, is analyzed to produce CELs and skeleton information,preferably both in binary and in color forms, as well as maskinformation (step 260). The results of step 260, preferably includingone or more of binary CELs, skeletons, color CELs and color skeletons,preferably are utilized in a learn process (step 270), to produce acomputer file reference representing an ideal electrical circuit to beinspected.

[0184] Reference is now made to FIGS. 5A-5D and FIG. 6, which may aid inunderstanding of the present invention:

[0185] FIGS. 5A-5C are simplified pictorial illustrations of examples ofoverlays, which may be combined together to comprise a representation ofan inspectable surface of an electrical circuit such as a BGA. In theexample shown, FIG. 5A is a simplified pictorial illustration of anoverlay indicating regions of copper conductor 280 and regions ofsubstrate 282. FIG. 5B is a simplified pictorial illustration of anoverlay indicating regions covered by translucent solder mask 284, andregions not covered by translucent solder mask 286. FIG. 5C is asimplified pictorial illustration of an overlay indicating regions ofgold plating 288 and regions that are not gold plated 290.

[0186]FIG. 5D is a simplified pictorial illustration of an example of aninspectable surface of an electrical circuit, for example an outer layerof a BGA, which may be comprised of the overlays of FIGS. 5A-5C, inwhich the following are shown: regions of copper conductor covered bysolder mask 292, regions of substrate covered by solder mask 294,regions of copper conductor coated by gold 296 and regions of baresubstrate 298, regions of bare copper 299.

[0187]FIG. 6 is a simplified pictorial illustration of the process ofcombining of the overlays of FIGS. 5A-5C to comprise a representation ofthe inspectable surface of FIG. 5D.

[0188] FIGS. 5A-5D and 6 generally are self-explanatory with referenceto the above description, particularly the description of FIG. 2.

[0189] Reference is now made to FIG. 7, which is a simplified flowchartillustration of a preferred method of operation of the binary CELproducer and skeleton producer 174 of FIG. 2. The method of FIG. 7comprises a preferred implementation of CEL production from CAM datainput which may be performed on a single overlay as shown in any ofFIGS. 5A, 5B or 5C, or on a superimposed image such as is shown in FIG.5D, so as to produce CELs for boundaries between various combinations ofmaterials in the electrical circuit layer as may be desired to produce acomputer file reference 130. Methods described in co-pending IsraelPatent Application 131092, filed Jul. 25, 1999, which has beenincorporated herein by reference, may be used for skeleton productionfrom raster data input.

[0190] The method of FIG. 7 preferably comprises the following steps:

[0191] Small pixels comprising the input raster image are grouped intobig pixels (step 300) wherein each big pixel preferably corresponds insize to an optical pixel in an optical inspection subsystem 100 (FIG.1A). Each big pixel preferably comprises a rectangular array of smallpixels. The small pixels preferably correspond in size to the subpixelresolution at which optical inspection subsystem 100 operates duringonline inspection and image processing of electrical circuits.Typically, the sub-pixel resolution image generation of an image ofobject, such as an electrical circuit being inspected, is performedgenerally as described in U.S. Pat. Nos. 5,774,572 and 5,774,573 toCaspi et al..

[0192] Reference is now additionally made to FIG. 8, which is asimplified pictorial illustration of a big pixel, comprising a pluralityof small pixels, useful in understanding the method of FIG. 7. In FIG. 8a single big pixel 375 is illustrated. Big pixel 375 comprises aplurality of small pixels 377, arranged in a rectangular array. The bigpixel 375 preferably comprises an array of 4×4 or 16×16 small pixels; anarray size of 10×10 is shown for purposes of simplicity of illustrationonly and is not meant to be limiting. Generally, the array size willcorrespond to the array size used by the vector/raster conversion unit160 (FIG. 2), as described above with reference to FIG. 2, whichpreferably corresponds to a sub-optical pixel definition employed in theoptical inspection subsystem 100.

[0193] The remaining steps of FIG. 7 preferably are performed once foreach big pixel, preferably in accordance with a pre-defined scanpattern, as is well-known in the art.

[0194] A difference of Gaussians (DOG) sign is determined at one vertexof each big pixel 375 (step 310). The DOG sign is the positive/negativesign of the second derivative of the intensity of an optical pixel atthe current point in a function of optical pixel intensities, andpreferably is chosen so that, if the optical intensity of the currentbig pixel is relatively dark the sign is positive, and otherwise it isnegative. DOG signs are indicative of an edge of an optical pixelthrough which an edge in the pattern on an article being inspectedpasses. Thus an edge passes between vertices of an optical pixel 375that have oppositely signed positive/negative DOG signs while no edgepasses between vertices having the same DOG sign.

[0195] The DOG sign may be determined at any of the four vertices 380,390, 400, and 410 as shown in FIG. 8. However, as will be describedbelow, for the sake of connectivity of CELs between adjoining bigpixels, the DOG point of only a single vertices is determined for eachbig pixel 375, and the DOG signs for other vertices are taken fromneighboring big pixels.

[0196] The DOG signs determined at the four vertices are referred toherein respectively as DOG sign 0, DOG sign 1, DOG sign 2, and DOG sign3 which correspond to vertices 380, 390, 400 and 410 respectively. Forthe sake of simplicity of description, the description of the steps ofFIG. 7 assumes that DOG sign 2 located at vertex 400 is used, but it isappreciated that a skilled person of the art would be able to choose adifferent DOG sign and would vary the remainder of the method of FIG. 7accordingly.

[0197] Methods of computing a DOGs in pixel images acquired during theinspection of an electrical circuit are well known in the art, and aredescribed, for example, in co-pending Israel Patent Application 131092,filed Jul. 25, 1999, which has been incorporated herein by reference.Methods for computing a DOG are also described in the following UnitedStates Patents, which have been incorporated herein by reference: U.S.Pat. No. 5,774,572 to Caspi; and U.S. Pat. No. 5,774,573 to Caspi et al.It is appreciated by persons skilled in the art that the DOG sign may becomputed alternatively, in a raster image, simply based on therelationship between two color populations contained in a big pixel. Ifone of the populations is lighter than the other than preferably, theDOG sign of the lighter population is negative and the DOG sign of thedarker population is positive. Determination of the DOG value preferablyis made by counting the number of dark small pixels in the current bigpixel, relative to its neighbors. In this manner, a complete DOGcomputation, as described in the references cited above, is notnecessary.

[0198] The values of two cross points are determined by the number ofsmall pixels at the edge for the current big pixel (step 320). The valueof a cross point refers to a value allocated for an edge 420, 430, 444or 450 of a big pixel 375 as a function of the point along the edge 420,430, 444 and 450 of a big pixel at which a transition occurs betweenlight and dark small pixels. The existence of a transition is indicatedby oppositely signed DOG signs at neighboring vertices.

[0199] It is appreciated that a cross point may be determined simply byidentifying where the small pixels along an edge change from a binary 0to binary 1, or vice versa. In FIG. 8, valued cross points, namely crosspoints for which a change in value occurs, are shown associated withedge 440 and edge 450. It is noted that there is no transition of smallpixels from light to dark (binary 0 to binary 1), along either of edges420 or 430. For tracking purposes, edges 420 and 430 preferably areassigned a cross point value, such as −1, indicating that no transitionof small pixels occurs along that edge. Each of the edges 440 and 450may be assigned a cross point value, indicating which small pixel alongthe corresponding edge the transition is found to occur. A preferreddata structure for representing CELs is described in Israel PatentApplication 131282, which has been incorporated herein by reference.

[0200] Preferably, for each big pixel, as will be described below, crosspoint values are determined for two edges only in a big pixel, whereinthe cross point value for each of the other edges in a big pixel aretaken from neighboring big pixels. For the sake of simplicity ofdescription, it is assumed that cross point values are determined foredge 440 and edge 450 in step 320, but it is appreciated that personsskilled in the art could choose another two edges, and the remainder ofthe method of FIG. 7 would vary accordingly.

[0201] Preferably, if more than one transition from light to dark, orvice versa, in small pixels is found on a given edge only one transitionsuch as, for example, the first transition, is used for that edge. Thefirst transition may be determined arbitrarily, for example along ahorizontal pixel edge as being the left most transition, and along avertical pixel edge as being the top most transition, or vise versa. Itis appreciated that, if the first transition is used, searching for anadditional transition on the edge preferably ceases. Additionally,continuity between adjoining big pixels of cross point values ismaintained by taking cross point values for two edges from neighboringbig pixels, in step 360 discussed below, as needed

[0202] Inasmuch as a DOG sign is computed for a single vertex of a bigpixel, DOG signs are determined for the three remaining vertices of thecurrent big pixel by taking the DOG values at vertices of neighboringpixels (step 330), it being appreciated that the DOG values atneighboring big pixels are determined and buffered before step 330 iscarried out.

[0203] Reference is now additionally made to FIG. 9, which is asimplified pictorial illustration of a big pixel and its neighbors,useful in understanding the method of FIG. 7. In FIG. 9 a current bigpixel 470, designated pixel Xi,Yi and having vertices 472, 474, 476 and478, and five neighboring pixels, designated pixels Xi+1,Yi 480,Xi+1,Yi−1 482, Xi,Yi−1 484, Xi−1,Yi−1 486, and Xi−1,Yi 488 are shown. Itwill be appreciated by persons skilled in the art that if the DOG valueat vertex 472 is determined for pixel 470, then the 3 remaining DOGsigns for vertices 474, 476 and 478 (corresponding to vertices 380, 390,and 410 in FIG. 8) are logically determined by, and therefore may bedetermined based on, DOG signs of the neighboring pixels. Thus, forexample the DOG signs of vertex 474 may be taken from pixel 484, the DOGsigns of vertex 476 may be taken from pixel 486 and the DOG signs ofvertex 478 may be taken from pixel 488.

[0204] A check is made as to whether all four DOG signs for the currentbig pixel are equally signed (step 340). If all four DOG signs areequally signed (positive/negative), thereby indicating that notransition from white to black occurs in the current big pixel, then noedge passes through current big pixel 375, and no CEL is assigned to thecurrent big pixel 375 (step 350). If not all four DOG signs are equallysigned, then the cross point values for the remaining edges are takenbased on the corresponding cross point values found in neighboring bigpixels. The determination of values for remaining cross points fromneighbors is self-explanatory with reference to the above discussion ofstep 330 and FIGS. 8 and 9.

[0205] If not all DOG signs are equal (positive/negative), then a CEL isassigned based on the cross point values as previously determined (step370). The end points of the CEL are based on cross point values, and avectorized direction preferably is assigned to a CEL is based on theorientation of the white and black regions in big pixel 375 relative tothe CEL. Referring again to FIG. 8, CEL 460 is based on cross pointsalong edges 440 and 450. A preferred data structure for a CEL includingits vector direction, is described in Israel Patent Application 131282which has been incorporated herein by reference.

[0206] Reference is now made to FIG. 10, which is a simplified flowchartillustration of a preferred method of operation of the color CEL/colorskeleton producer 178 of FIG. 2. Except as otherwise stated, the methodof FIG. 10 is similar to the method of FIG. 7 and is to be understoodwith reference to the above discussion of FIG. 7. It is appreciated thatthe input to FIG. 10 preferably comprises a color raster image in whicheach pixel of the raster is assigned a color, preferably one of apredetermined number of colors corresponding to a homogeneous colorpopulation that is associated with a combination of overlays ofmaterials on the surface of an article to be inspected. The assignmentof a color is preferably performed by operation of rules as describedabove with reference to superimposer 170 (FIG. 2).

[0207] The method of FIG. 10 preferably comprises the following steps:

[0208] After performing step 300, as described above with reference toFIG. 7, the number of different colors represented by the small pixelsmaking up the current big pixel is determined and a decision is madebased on the number of colors present in the big pixel (step 490):

[0209] 1. If the number of colors in the current big pixel is 1, no edgeexists in the current big pixel and no CEL is assigned to the currentbig pixel (step 350).

[0210] 2. If the number of colors in the current big pixel is greaterthan 2, a junction is assigned to the current big pixel (step 500).Junctions are described in co-pending Israel Patent Application 131092,filed Jul. 25, 1999, which has been incorporated herein by reference.

[0211] 3. If the number of colors in the current big pixel is equal to2, the method preferably continues at step 1310 in a similar manner asin the method of FIG. 7, (step 310). It is appreciated that, in thiscase, a color DOG or CDOG, is determined. In the CDOG both color andrelative pixel intensity are considered. The CEL assigned in step 1370preferably comprises a color CEL including information on the two colorsin the current big pixel, typically as described in co-pending IsraelPatent Application 131092, filed Jul. 25, 1999, referred to above.

[0212] It is appreciated that because the assignment of a sign to a CDOGtakes into account the color, it is necessary to apply consistent logicin determining whether such a sign is positive or negative. Thus inaccordance with a preferred embodiment of the invention, the sign,positive or negative, is determined as a function of a color, preferablyaccording to the following hierarchy:

[0213] 1. gold

[0214] 2. copper

[0215] 3. solder mask over metal

[0216] 4. solder mask over substrate

[0217] 5. bare substrate

[0218] When a big pixel includes colors representative of any of the twoof the above materials, the material that is higher in the hierarchypreferably is assigned a negative CDOG value, while the material lowerin the hierarchy is assigned a positive CDOG value. For example, if abig pixel includes small pixels representative of gold and solder maskover substrate, the vertices of the big pixel are assigned a negativeCDOG value where the small pixels of gold are located, while thevertices of the big pixel are assigned a positive CDOG value where smallpixels of solder mask over substrate are located.

[0219] It is appreciated that steps 1310, 1320, and 1360 are similar tosteps 310, 320, and 360 of FIG. 7 respectively; steps 1330, 1340, and1370 correspond to steps 330, 340, and 370, respectively, of FIG. 7,with the use of CDOG in place of DOG.

[0220] It is appreciated that various features of the invention whichare, for clarity, described in the contexts of separate embodiments mayalso be provided in combination in a single embodiment. Conversely,various features of the invention which are, for brevity, described inthe context of a single embodiment may also be provided separately or inany suitable subcombination.

[0221] It will be appreciated by persons skilled in the art that thepresent invention is not limited by what has been particularly shown anddescribed hereinabove. Rather the scope of the invention is defined onlyby the claims which follow:

What is claimed is:
 1. An electrical circuit inspection systemcomprising: an optical subsystem for optically inspecting an electricalcircuit and providing an inspection output identifying more than twodifferent types of regions; and an analysis subsystem for analyzing saidinspection output, said analyzing including comparing said inspectionoutput with a computer file reference identifying more than twodifferent types of regions.
 2. An electrical circuit inspection systemaccording to claim 1 and wherein said optical subsystem is capable ofoptically inspecting more than one layer of an electrical circuit andsaid more than two different types of regions include regions at morethan one layer of said electrical circuit.
 3. An electrical circuitinspection system according to claim 1 or claim 2 and wherein said morethan two different types of regions include an exposed metal region, ametal region covered by a translucent material, an exposed substrate anda substrate covered by said translucent material.
 4. An electricalcircuit inspection system according to claim 3 and wherein saidtranslucent material is a solder mask.
 5. An electrical circuitinspection system according to claim 3 and wherein said translucentmaterial is a polyamide layer.
 6. An electrical circuit inspectionsystem according to claim 1 or claim 2 and wherein said more than twodifferent types of regions include an exposed first metal region, afirst metal region covered by a translucent material, an exposed secondmetal region, a second metal region covered by a translucent material,an exposed substrate and a substrate covered by said translucentmaterial.
 7. An electrical circuit inspection system according to claim6 and wherein said translucent material is a solder mask.
 8. Anelectrical circuit inspection system according to claim 6 and whereinsaid translucent material is a polyamide layer.
 9. An electrical circuitinspection system according to any of the preceding claims and whereinsaid computer file reference identifying more than two different typesof regions comprises a composite of multiple computer files, eachrepresenting a different layer of said electrical circuit.
 10. Anelectrical circuit inspection system according to any of the precedingclaims and wherein said computer file reference identifying more thantwo different types of regions comprises an overlay of multiple computerfiles, each representing a different layer of said electrical circuit.11. An electrical circuit inspection system according to any of thepreceding claims and wherein said computer file reference identifyingmore than two different types of regions comprises multiple computerfiles, each representing a different layer of said electrical circuit,superimposed in mutual registration.
 12. An electrical circuitinspection system according to any of the preceding claims and whereinsaid computer file reference comprises a computer file of at least onemetal layer and at least one layer of a translucent material overlyingsaid at least one metal layer, superimposed in mutual registration. 13.An electrical circuit inspection system according to any of thepreceding claims and wherein said computer file reference is apolychromatic reference.
 14. An electrical circuit inspection systemaccording to any of the preceding claims and wherein said inspectionoutput is a polychromatic output.
 15. An electrical circuit inspectionsystem according to any of the preceding claims and wherein saidcomputer file reference comprises at least one CAM file.
 16. Apparatusfor constructing a computer file reference identifying more than twodifferent types of regions on an electrical circuit comprising asuperimposer for superimposing in mutual registration at least twocomputer files, each representing a different portion of said electricalcircuit.
 17. Apparatus according to claim 16 and wherein the differenttypes of regions are optically distinguishable.
 18. Apparatus accordingto either of claims 16 and 17 and wherein the portion is a layer of theelectrical circuit, and a plurality of layers form an inspectablesurface of the electrical circuit.
 19. Apparatus for constructing acomputer file reference identifying more than two different types ofregions on an electrical circuit according to claim 16 and wherein saidmore than two different types of regions include an exposed metalregion, a metal region covered by a translucent material, an exposedsubstrate and a substrate covered by said translucent material. 20.Apparatus for constructing a computer file reference according to claim19 and wherein said translucent material is a solder mask.
 21. Apparatusfor constructing a computer file reference according to claim 19 andwherein said translucent material is a polyamide layer.
 22. Apparatusfor constructing a computer file reference according to claim 16 orclaim 19 and wherein said more than two different types of regionsinclude an exposed first metal region, a first metal region covered by atranslucent material, an exposed second metal region, a second metalregion covered by a translucent material, an exposed substrate and asubstrate covered by said translucent material.
 23. Apparatus forconstructing a computer file reference according to claim 22 and whereinsaid translucent material is a solder mask.
 24. Apparatus forconstructing a computer file reference according to claim 22 and whereinsaid translucent material is a polyamide layer.
 25. Apparatus forconstructing a computer file reference according to any of the precedingclaims 16-24 and wherein said computer file reference identifying morethan two different types of regions comprises a composite of multiplecomputer files, each representing a different layer of said electricalcircuit.
 26. Apparatus for constructing a computer file referenceaccording to any of the preceding claims 16-25 and wherein said computerfile reference identifying more than two different types of regionscomprises an overlay of multiple computer files, each representing adifferent layer of said electrical circuit.
 27. Apparatus forconstructing a computer file reference according to any of the precedingclaims 16-26 and wherein said computer file reference identifying morethan two different types of regions comprises multiple computer files,each representing a different layer of said electrical circuit,superimposed in mutual registration.
 28. Apparatus for constructing acomputer file reference according to any of the preceding claims 16-27and wherein said computer file reference comprises a computer file of atleast one metal layer and at least one layer of a translucent materialoverlying said at least one metal layer, superimposed in mutualregistration.
 29. Apparatus for constructing a computer file referenceaccording to any of claims 16-28 and wherein said computer filereference comprises at least one CAM file.
 30. A computer file referenceuseful in an electrical circuit inspection system and comprising atleast one computer originated computer file representing more than twodifferent types of regions in said electrical circuit
 31. A computerfile reference according to claim 30 and wherein the types of regionsare optically distinguishable.
 32. A computer file reference accordingto claim 30 and comprising at least one computer originated computerfile representing more than two different types of regions in saidelectrical circuit, wherein each region is one of a material formingpart of an electrical circuit, a composite of at least two materialsforming an electrical circuit.
 33. A computer file reference accordingto claim 30 and wherein said at least one computer file comprises acombination of multiple computer files, each representing a differentlayer of an electrical circuit, said reference identifying more than twodifferent types of regions.
 34. A computer file reference according toclaim 30 and wherein said at least one computer file is derived frommultiple computer files, each representing a different layer of anelectrical circuit, said reference identifying more than two differenttypes of regions.
 35. A computer file reference according to claim 30and wherein said reference comprises an overlay of multiple computerfiles, each representing a different layer of said electrical circuit.36. A computer file reference according to any of the preceding claims30-35 and wherein said computer file reference identifying more than twodifferent types of regions comprises multiple computer files, eachrepresenting a different layer of said electrical circuit, superimposedin mutual registration.
 37. A computer file reference according to anyof the preceding claims 30-36 and comprising a computer file of at leastone metal layer and at least one layer of a translucent materialoverlying said at least one metal layer, superimposed in mutualregistration.
 38. A computer file reference according to any of thepreceding claims 30-37 and wherein said computer file reference is apolychromatic reference.
 39. A computer file reference according to anyof the preceding claims 30-38 and wherein said inspection output is apolychromatic output.
 40. A method for determining a contour element(cel) in each of a plurality of big pixels, each big pixel comprising anarray of small pixels, the method comprising: assigning an array ofsmall pixels to each big pixel; performing the following steps for eachbig pixel: computing a difference of gradients sign (DOG sign) at onevertex of the big pixel; determining two cross points along two edges ofthe big pixel, each cross point representing a value crossover betweenpixels having a first value and pixels having a second value;determining DOG signs for remaining vertices of the big pixel based onDOG values assigned to neighboring pixels of the big pixel; and if atleast one DOG sign at one vertex of the big pixel differs from at leastone DOG sign at one other vertex of the big pixel: determining remainingcross points along remaining edges of the big pixel; and assigning a celbased on a result of the determining remaining cross points step.
 41. Amethod for determining a color contour element (cel) in each of aplurality of big pixels, each big pixel comprising an array of smallpixels, the method comprising: assigning an array of small pixels toeach big pixel; performing the following steps for each big pixel:determining a number of colors of small pixels comprised in the bigpixel; if the number of colors is equal to one, concluding the method;if the number of colors is greater than two, indicating that a junctionexists in the big pixel and terminating the method; otherwise, thenumber of colors being two, performing the following steps: computing adifference of gradients sign (DOG sign) at one vertex of the big pixel;determining two cross points along two edges of the big pixel, eachcross point representing a value crossover between pixels having a firstvalue and pixels having a second value; determining DOG signs forremaining vertices of the big pixel based on DOG values assigned toneighboring pixels of the big pixel; and if at least one DOG sign at onevertex of the big pixel differs from at least one DOG sign at one othervertex of the big pixel: determining remaining cross points alongremaining edges of the big pixel; and assigning a color cel based on aresult of the determining remaining cross points step and on the colorsof small pixels comprised in the big pixel.
 42. An electrical circuitinspection method comprising: optically inspecting an electrical circuitand providing an inspection output identifying more than two differenttypes of regions; and analyzing said inspection output, said analyzingincluding comparing said inspection output with a computer filereference identifying more than two different types of regions.
 43. Amethod for constructing a computer file reference identifying more thantwo different types of regions on an electrical circuit comprisingsuperimposing in mutual registration at least two computer files, eachrepresenting a different layer of said electrical circuit.
 44. Apparatusfor determining a contour element (cel) in each of a plurality of bigpixels, each big pixel comprising an array of small pixels, theapparatus comprising: a pixel assigner operative to assign an array ofsmall pixels to each big pixel; a cel determiner operative, for each bigpixel: to compute a difference of gradients sign (DOG sign) at onevertex of the big pixel; to determine two cross points along two edgesof the big pixel, each cross point representing a value crossoverbetween pixels having a first value and pixels having a second value; todetermine DOG signs for remaining vertices of the big pixel based on DOGvalues assigned to neighboring pixels of the big pixel; and if at leastone DOG sign at one vertex of the big pixel differs from at least oneDOG sign at one other vertex of the big pixel: to determine remainingcross points along remaining edges of the big pixel; and to assign a celbased on a result of the determining remaining cross points step. 45.Apparatus for determining a color contour element (cel) in each of aplurality of big pixels, each big pixel comprising an array of smallpixels, the apparatus comprising: and assigner operative to assign anarray of small pixels to each big pixel; a color cel determineroperative, for each big pixel: to determine a number of colors of smallpixels comprised in the big pixel; if the number of colors is equal toone, to conclude the method; if the number of colors is greater thantwo, to indicate that a junction exists in the big pixel and terminatingthe method; otherwise, the number of colors being two: to compute adifference of gradients sign (DOG sign) at one vertex of the big pixel;to determine two cross points along two edges of the big pixel, eachcross point representing a value crossover between pixels having a firstvalue and pixels having a second value; to determine DOG signs forremaining vertices of the big pixel based on DOG values assigned toneighboring pixels of the big pixel; and if at least one DOG sign at onevertex of the big pixel differs from at least one DOG sign at one othervertex of the big pixel: to determine remaining cross points alongremaining edges of the big pixel; and to assign a color cel based on aresult of the determining remaining cross points step and on the colorsof small pixels comprised in the big pixel.
 46. An electrical circuitinspection system comprising: an optical subsystem for opticallyinspecting an electrical circuit and providing an inspection outputidentifying edges between at least two different regions in theelectrical circuit; and an analysis subsystem for analyzing saidinspection output, said analyzing including comparing said inspectionoutput with a computer file reference identifying edges between at leasttwo different regions.
 47. An electrical circuit inspection systemaccording to claim 46 and wherein said optical subsystem is capable ofoptically inspecting more than one layer of an electrical circuit andsaid more than two different regions include regions at more than onelayer of said electrical circuit.
 48. An electrical circuit inspectionsystem according to claim 46 or claim 47 and wherein said more than twodifferent regions include an exposed metal region, a metal regioncovered by a translucent material, an exposed substrate and a substratecovered by said translucent material.
 49. An electrical circuitinspection system according to claim 48 and wherein said translucentmaterial is a solder mask.
 50. An electrical circuit inspection systemaccording to claim 48 and wherein said translucent material is apolyamide layer.
 51. An electrical circuit inspection system accordingto claim 46 or claim 47 and wherein said more than two different regionsinclude an exposed first metal region, a first metal region covered by atranslucent material, an exposed second metal region, a second metalregion covered by a translucent material, an exposed substrate and asubstrate covered by said translucent material.
 52. An electricalcircuit inspection system according to claim 51 and wherein saidtranslucent material is a solder mask.
 53. An electrical circuitinspection system according to claim 51 and wherein said translucentmaterial is a polyamide layer.
 54. An electrical circuit inspectionsystem according to any of claims 46-53 and wherein said computer filereference identifying more than two different regions comprises acomposite of multiple computer files, each representing a differentlayer of said electrical circuit.
 55. An electrical circuit inspectionsystem according to any of claims 46-54 and wherein said computer filereference identifying more than two different regions comprises anoverlay of multiple computer files, each representing a different layerof said electrical circuit.
 56. An electrical circuit inspection systemaccording to any of claims 46-55 and wherein said computer filereference identifying more than two different regions comprises multiplecomputer files, each representing a different layer of said electricalcircuit, superimposed in mutual registration
 57. An electrical circuitinspection system according to any of claims 46-56 and wherein saidcomputer file reference comprises a computer file of at least one metallayer and at least one layer of a translucent material overlying said atleast one metal layer, superimposed in mutual registration.
 58. Anelectrical circuit inspection system according to any of claims 46-57and wherein said computer file reference is a polychromatic reference.59. An electrical circuit inspection system according to any of claims46-58 and wherein said inspection output is a polychromatic output. 60.An electrical circuit inspection system according to any of claims 46-59and wherein said computer file reference comprises at least one CAMfile.
 61. An electrical circuit inspection system according to any ofclaims 46-60 and wherein said computer file reference comprises aplurality of CAM files.
 62. A method for electrical circuit inspectioncomprising: optically inspecting an electrical circuit and providing aninspection output identifying edges between at least two differentregions in the electrical circuit; and analyzing said inspection output,said analyzing including comparing said inspection output with acomputer file reference identifying edges between at least two differentregions.
 63. A method according to claim 62 and wherein said opticallyinspecting includes optically inspecting more than one layer of anelectrical circuit and said more than two different regions includeregions at more than one layer of said electrical circuit.
 64. A methodaccording to claim 62 or claim 63 and wherein said more than twodifferent regions include an exposed metal region, a metal regioncovered by a translucent material, an exposed substrate and a substratecovered by said translucent material.
 65. A method according to claim 64and wherein said translucent material is a solder mask.
 66. A methodaccording to claim 64 and wherein said translucent material is apolyamide layer.
 67. A method according to claim 62 or claim 63 andwherein said more than two different regions include an exposed firstmetal region, a first metal region covered by a translucent material, anexposed second metal region, a second metal region covered by atranslucent material, an exposed substrate and a substrate covered bysaid translucent material.
 68. A method according to claim 67 andwherein said translucent material is a solder mask.
 69. A methodaccording to claim 67 and wherein said translucent material is apolyamide layer.
 70. A method according to any of claims 62-69 andwherein said computer file reference identifying more than two differentregions comprises a composite of multiple computer files, eachrepresenting a different layer of said electrical circuit.
 71. A methodaccording to any of claims 62-70 and wherein said computer filereference identifying more than two different regions comprises anoverlay of multiple computer files, each representing a different layerof said electrical circuit.
 72. A method according to any of claims62-71 and wherein said computer file reference identifying more than twodifferent regions comprises multiple computer files, each representing adifferent layer of said electrical circuit, superimposed in mutualregistration.
 73. A method according to any of claims 62-72 and whereinsaid computer file reference comprises a computer file of at least onemetal layer and at least one layer of a translucent material overlyingsaid at least one metal layer, superimposed in mutual registration. 74.A method according to any of claims 62-73 and wherein said computer filereference is a polychromatic reference.
 75. A method according to any ofclaims 62-74 and wherein said inspection output is a polychromaticoutput.
 76. A method according to any of claims 62-75 and wherein saidcomputer file reference comprises at least one CAM file.
 77. A methodaccording to any of claims 62-76 and wherein said computer filereference comprises a plurality of CAM files.